Nonetheless, if the frequency of the clock signal provided to a multiplexer is high, the operation of the multiplexer may become unstable. H11-17636).Ī further technology is known in which a converter converts parallel signals into a serial signal (for example, refer to Japanese Laid-Open Patent Publication No. For example, a technology is known in which multiple stages of multiplexers that convert 2 parallel signals into a serial signal according to the value of a clock signal are disposed such that multiplexers farther downstream have clock signals of higher frequencies, whereby staged multiplexing is performed (for example, refer to Japanese Laid-Open Patent Publication No.
BACKGROUNDĬonventionally in the communication of data, a data transmission apparatus may use a multiplexer to convert parallel signals into a serial signal for transmission to a receiving apparatus. The embodiments discussed herein are related to a parallel-to-serial converter circuit. 10, 2012, the entire contents of which are incorporated herein by reference. This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No.
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